Chemical-mechanical planarization (“CMP”) processes remove material from the surface of a wafer in the production of ultra-high density integrated circuits. In a typical CMP process, a wafer is pressed against a polishing pad in the presence of a slurry under controlled chemical, pressure, velocity, and temperature conditions. The slurry solution generally contains small, abrasive particles that abrade the surface of the wafer, and chemicals that etch and/or oxidize the surface of the wafer. The polishing pad is generally a planar pad made from a relatively porous material such as blown polyurethane. Thus, when the pad and/or the wafer moves with respect to the other material is removed from the surface of the wafer by the abrasive particles (mechanical removal) and by the chemicals in the slurry (chemical removal).
FIG. 1 schematically illustrates a conventional CMP machine 10 with a platen 20, a wafer carrier 30 a polishing pad 40, and a slurry 44 on the polishing pad 40. The platen 20 has a surface 22 upon which the polishing pad 40 is positioned. A drive assembly 26 rotates the platen 20 as indicated by arrow A and/or reciprocates the platen back and forth as indicated by arrow B. The motion of the platen 20 is imparted to the pad 40 because the polishing pad 40 frictionally engages the upper surface 22 of the platen 20. The wafer carrier 30 has a lower surface 32 to which a wafer 50 may be attached, or the wafer 50 may be attached to a resilient pad 34 positioned between the wafer 50 and the lower surface 32. The wafer carrier 30 may be a weighted, free-floating wafer carrier, or an actuator assembly 36 may be attached to the wafer carrier 30 to impart axial and rotational motion, as indicated by arrows C and D, respectively.
In the operation of the conventional planarizer 10, the wafer 50 is positioned face-downward against the polishing pad 40, and then the platen 20 and the wafer carrier 30 move relative to one another. As the face of the wafer 50 moves across the planarizing surface 42 of the polishing pad 40, the polishing pad 40 and the slurry 44 remove material from the wafer 50.
CMP processes must consistently and accurately produce a uniform, planar surface on the wafer because it is important to accurately focus circuit patterns on the wafer. As the density of integrated circuits increases, currently lithographic techniques must accurately focus the critical dimensions of photo-patterns to within a tolerance of approximately 0.35-0.5 μm. Focusing the photo-patterns to such small tolerances, however, is very difficult when the distance between the emission source and the surface of the wafer varies because the surface of the wafer is not uniformly planar. In fact, when the surface of the wafer is not uniformly planar, several devices on the wafer may be defective. Thus, CMP processes must create a highly uniform, planar surface.
In the competitive semiconductor industry, it is also highly desirable to maximize the throughput of CMP processes to produce accurate, planar surfaces as quickly as possible. The throughput of CMP processes is a function of several factors, two of which are the ability to accurately stop the CMP process at a desired endpoint and the rate at which material is removed from the wafer (the “polishing rate”). Accurately stopping the CMP process at a desired endpoint is important to maintaining a high throughput because the thickness of the dielectric layer must be within and acceptable range; if the thickness of the dielectric layer is not within an acceptable range, the wafer must be re-planarized until it reaches the desired endpoint. Maintaining a high, consistent polishing rate is also important to sustaining a high throughput because the polishing rate determines the length of the planarization process. Thus, it is desirable to stop the CMP process at the desired endpoint and to maintain a high polishing rate.
FIGS. 2A and 2B illustrate existing techniques to endpoint CMP processing using polish-stop layers. Referring to FIG. 2A, a stop-on-feature wafer 50(a) has a substrate 60 and a number of device features 62 formed on the substrate 60. A polish-stop layer 80 is deposited over the substrate 60 and the device features 62, and an insulative layer 70 is deposited on the polish-stop layer 80. The polish-stop layer 80 has a lower polishing rate than that of the insulative layer 70. Referring to FIG. 2(B), an interconnect wafer 50(b) has a substrate 60, a device feature 62 formed in the substrate 60, an insulative layer 70 deposited over the substrate 60, and a polish-stop layer 80 deposited on the insulation layer 70. A via 74 is cut through the insulative layer 70 and the polish-stop layer 80, and a conductive layer 90 is deposited into the via 74 and over the polish-stop layer 80. The portion of the conductive layer 90 in the via 74 forms an interconnect 92 to the device feature 62. In case of an interconnect wafer, the polish-stop layer 80 also has a lower polishing rate than that of the conductive layer 90.
In operation, the insulative layer 70 of the stop-on-feature wafer 50(a) or the conductive layer 90 of the interconnect wafer 50(b) is planarized until the polishing pad (shown in FIG. 1) engages the top surface 81 of the polish-stop layer 80. Since the polishing rate of the polish-stop layer 80 is lower than that of the upper layer, the polish-stop layer resists planarization under certain operating parameters to reduce the polishing rate at a desired endpoint.
U.S. Pat. No. 5,246,884 to Jaso et al. discloses using diamond or diamond-like carbon (“DLC”) as a chemical-mechanical polish stop. In particular, a metallized semiconductor chip is coated with a first layer of silicon dioxide followed by a second layer of diamond or DLC as an etch stop. The DLC is deposited at about 75° C. to about 350° C. to form a layer of DLC with a thickness of 750 Å to 1000 Å. U.S. Pat. No. 5,246,884 discloses that DLC effectively stops planarization with softer polishing pads, such as an IC-40 or an IC-60 polishing pad, but that no difference in the thickness uniformly or planarity was observed when harder polishing pads were used to planarize wafers. U.S. Pat. No. 5,246,884 discloses that diamond or DLC works well as an etch stop with soft polishing pads because these substances are exceptionally hard.
One problem with DLC polish-stop layers is that they do not effectively endpoint CMP processing with hard polishing pads. Hard polishing pads are often the pad of choice for many CMP applications; compared to softer polishing pads, hard polishing pads reduce dishing over large features, withstand higher down forces, and resist wear better. Hard polishing pads, however, effectively planarize DLC because the carbon atoms are bonded to each other and to adjacent hydrogen atoms in a manner that prevents the carbon atoms from moving with respect to each other and along substantially parallel, horizontal planes. Thus, because hard pads effectively planarize DLC, it would be desirable to make polish-stop layer from a material that effectively endpoints CMP processing with hard polishing pads.
Another problem with DLC polish-stop layers is that they are relatively time consuming to deposit on and remove from the wafers. Polish-stop layers made from DLC are deposited to a thickness of approximately 750 Å to approximately 1000 Å. As with any material; the process time to deposit a layer of DLC increases with increasing layer thickness. Moreover, in the case of interconnect wafers, the DLC layers is also cleaned from the surface of the wafer after the CMP process is finished to accommodate subsequent processing of the wafer. Thus, since the time to deposit and clean material increases with increasing layer thickness, it is desirable to reduce the thickness of the polish-stop layer without significantly impairing its effectiveness.